1. Field of the Invention
The present invention relates to a multiprocessor system and a microprocessor constituting the same, particularly, it relates to improvement of byte polarity processing of data.
2. Description of the Prior Art
When data are exchanged between a microprocessor and a memory, the data are generally inputted and/or outputted in every division of a certain number of bits. In the following, the case wherein the 32-bit microprocessor deals with 32-bit data will be described as an example. The 32-bit microprocessor divides the 32-bit data into four parts by one byte (8 bits) a part. FIG. 1 is an explanatory view showing the data exchange between the microprocessor and the memory. At this time, one byte in the higher position is called MSB (Most Significant Byte) and that in the lower position is called LSB (Least Significant Byte). As shown in FIG. 1, when data are exchanged with the memory, there are two systems, one is called a big endian system (hereinafter referred to as BE system) and the other is called a little endian system (hereinafter referred to as LE system). For example, when the data are inputted and/or outputted, in the BE system, they are written successively from the assigned address in the memory to four sequential addresses in the order from the byte on the MSB side to the higher address. Conversely, in the LE system, they are written successively in the order from the byte on the LSB side to the higher address. The system by which the data are inputted and/or outputted is set for each microprocessor, which is referred to as a byte polarity of the microprocessor.
Now, in a multiprocessor system wherein a plurality of microprocessors are connected by a same system bus, respective microprocessors share a certain area (shared memory area) of a main memory connected to the system bus to communicate therebetween. FIG. 2 is a block diagram showing the relationship between the microprocessor and a main memory of a conventional multiprocessor system, wherein when data are sent from the microprocessor (A) to the microprocessor (B) connected via a system bus, the former writes the data in a shared memory area of the main memory (MM) and the latter reads the written data therefrom.
At this time, when data are exchanged between the microprocessors having different byte polarities, the compatibility of the data must be maintained. For examples, when the microprocessor of the BE system reads the data of plural byte lengths in the shared memory area written by the microprocessor of the LE system, the former must reverse the byte order of the data being read. The rearrangement is generally executed by softwares. The microprocessor capable of executing data rearrangement by one command by preparing the data rearrangement command has also been developed.
In the multiprocessor system using two microprocessors whose byte polarities are different each other, it must be determined and processed whether the rearrangement of byte order of the data is necessary when accessing the memory. If this is processed by the softwares, the number of commands is increased, which accordingly makes an overhead of the microprocessor larger and delays the whole execution speed. In addition, a problem occurs that the programmer who develops an operation system of the multiprocessor system has to prepare for the data byte order rearrangement routine.